IRAMS10UP60A Series

1 Plug N DriveTM for Appliance Motor F, Gate Drivers and Bootstrap Diodes. • Monitor • and Fully Isolated Low VCE (on) Non Punch Through lockout for all Matched delay for all Low side IGBT emitter pins for current conrol • input logic • logic • Lower di/dt gate driver for better noise is an Power Module developed and optimized for motor control in appliance such as washing machines and Plug N offers an extremely compact, high AC in a single isolated package for a very simple design. A built-in monitor and along with the IGBTs and lockout function, deliver high level of and of the bootstrap diodes for the high-side driver section, and the single polarity required to drive the internal simplify the of the module and deliver further Maximum Max. Value Maximum IGBT Blocking Voltage 600 V+ Positive Bus Input Voltage 450 IO @ TC= 25°C RMS Phase Current 10 IO @TC =100°C RMS Phase Current 5 Ipk Maximum Peak Phase Current 15 Fp Maximum PWM Carrier Frequency 20 kHz Pd Maximum Power per Phase 20 W Viso Isolation Voltage (1min) 2000 VRMS TJ (IGBT & Diodes) Operating Junction Range -40 to +150 TJ (Driver IC) Operating Junction Range -40 to +150 T Mounting torque Range (M3 screw) 0.8 to 1.0 Schematic - VS1 24 HO1 25 VB1 1 VCC 2 HIN1 3 HIN2 4 HIN3 5 (12) VRW (14) VRV (13) VB1 (7) U, VS1 (8) VB2 (4) V, VS2 (5) VB3 (1) W, VS3 (22) VSS Rg3 16 LO3 14 LO2 (15) HIN2 (16) HIN3 (20) V Section @ TJ = Section Switching Parameter Min Typ Max Units Eon Turn-On Switching Loss --- 200 235 Eoff Turn-Off Switching Loss --- 75 100 Etot Total Switching Loss --- 275 335 Turn-on Swtiching Loss --- 300 360 Turn-off Switching Loss --- 135 165 Etot Total Switching Loss --- 435 Reverse Recovery 30 40 µJ trr Diode Reverse Recovery time --- 100 145 Bias Safe Operating Circuit Safe Operating Area 10 --- --- µs FULL IC=5A, VDD=+15V to 0V See losses include "tail" and diode reverse to 0V See V + =400V VDD=15V, IF=5A, Parameter Min Typ Max Units to case thermal each IGBT under inverter 4.2 4.7 to case thermal each Diode under inverter 5.5 6.5 case to 0.1 --- greased surface. Heatsink compound thermal - Parameter Min Typ Max Units Breakdown --- --- V VIN=0V, / Coeff. Of 0.57 --- - 1.7 2.0 IC=5A TJ=25°C, 2.0 2.4 IC=5A 5 15 VIN=5V, 10 40 VIN=5V, Gate -- 50 µA VIN=5V, 1.8 2.35 IC=5A --- 1.3 1.7 IC=5A, Gate Voltage Collector Forward Voltage Operating Driver logic timing diagram is shown in Figure 1. For proper operation the device should be used within All voltages are absolute to VSS. The VS offset is tested with all supplies biased at 15V (Note 1). All input pin (VIN ) and ITRIP are clamped with a 5.2V zener diode and pull-up resistor Min Max High side floating supply voltage VS+12 High side floating supply offset voltage Note 2 450 VDD Low side and logic fixed supply voltage 12 20 VITRIP T/ITRIP input voltage VSS VSS+5 VIN Logic input voltage LIN, HIN VSS VSS+5 Driver (VCC, unless otherwise The VIN and IIN are to VSS and are to all six channels. (Note Maximum Ratings Driver Maximum Ratings indicate limits beyond which damage to the device may occur. All voltage are absolute voltages to (Note Min Max High Side offset voltage -0.3 600 V VB1,2,3 High Side floating supply voltage -0.3 20 V VDD Low Side and logic fixed supply voltage -0.3 20 V VIN Input voltage LIN, HIN, T/ITRIP -0.3 7 V TJ Juction -40 150 Min Typ Max Positive going input threshold 3.0 --- --- V VIN,th- Negative going input threshold --- --- 0.8 V IQBS Quiescent VBS supply current --- 70 120 µA IQCC Quiscent VCC supply current --- 1.6 2.3 mA ILK Offset Supply Leakage Current --- --- 50 µA IIN+ Input bias current (OUT=LO) --- 100 220 µA IIN+ Input bias current (OUT=HI) --- 200 300 ITRIP threshold Voltage (OUT=HI or OUT=LO) 3.85 4.3 4.75 and VBS supply going and VBS supply 11.1 11.6 VCC and VBS supply going 5 Note 3: The Maximum sense voltage at the T/ITRIP terminal under normal operating is 3.3V. Built-in NTC - 1: For more details, see IR21365 data 2: Logic for Vs from V--5V to V-+600V. Logic stata held for VS from V--5V to V--VBS. (Please refer to DT97-3 for more Min Typ Max Units TON Input to output turn-on delay time (see fig.11) - 470 - ns TOFF Input to output turn-off delay time (see fig. 11) - 615 - ns DT Dead Time - 300 - T/ITrip to six switch to turn-off delay (see fig. 2) - 750 - Post ITrip to six switch to turn-off clear time (see fig. 2) - 9 - ms Typ Units 100 +/- 5% kΩ TC = 25°C R125 2.522 + 17.3 % /- 14.9% kΩ TC = 125°C B (25-50°C) 4250 +/- 3% k R2 = R1e [B(1/T2 - / 125 °C 1 mW/°C TC = (21) VSS Io=1A, VD=9V, unless otherwise Timing 4: The shaded area indicates that both high-side and low-side switches are off and therefore the output voltage would be by the direction of current flow in the U,V,W 0 0 1 Vbus 0 1 0 0 0 1 1 X 1 X X 7 Note 5: The shaded area indicates that both high-side and low-side switches are off and therefore the output voltage would be by the direction of current flow in the 2. T/ITrip Timing Pin-Out Name VB3 High Side Floating Supply Voltage 3 2 W,VS3 Output 3 - High Side Floating Supply Offset Voltage 3 na none 4 VB2 High Side Floating Supply voltage 2 5 V,VS2 Output 2 - High Side Floating Supply Offset Voltage 6 na none 7 VB1 High Side Floating Supply voltage 1 8 U,VS1 Output 1 - High Side Floating Supply Offset Voltage 9 na none 10 V+ Positive Bus Input na none 12 LE1 Low Side Emitter - Phase 1 13 LE2 Low Side Emitter - Phase 2 14 LE3 Low Side Emitter - Phase 3 15 HIN1 Logic Input High Side Gate Driver - Phase 1 16 HIN2 Logic Input High Side Gate Driver - Phase 2 17 HIN3 Logic Input High Side Gate Driver - Phase 3 18 LIN1 Logic Input Low Side Gate Driver - Phase 1 19 LIN2 Logic Input Low Side Gate Driver - Phase 2 20 LIN3 Logic Input Low Side Gate Driver - Phase 3 21 T/Itrip Monitor and Shut-down Pin 22 VCC +15V Main Supply 23 VSS Negative Main V IC DC SENSING CAN USE A SINGLE SENSE RESISTOR OR SENSING AS bus should be mounted as close to the module bus terminals as possible to reduce ringing and EMI problems. high frequency ceramic capacitor mounted close to the module pins will further improve In order to provide good between VCC-Gnd and VB-VSS the shown connected be- tween these terminals should be located very close to the module pins. high frequency are strongly Value of the depends upon the switching Their selection should be made based on IR design tip DN 98-2a, note AN-1044 or Figure 9. 4. Low shunt resistors shuld be used for phase leg current sensing. the length of the traces be- tween pins 12, 13 and 14 to the shunt resistors should be kept as small as sense signal can be obtained from external hardware detecting excessive current in 3. Maximum phase current as function of switching Tj=150°C, 4. Maximum phase current as function of Tj=150°C, Tc=100°C, 2 4 6 8 10 12 14 16 18 20 PWM Switching Frequency R M S (A ) 10 100 Motor Current Frequency R M S Ph as e (A ) . 12 kHz 16 kHz 20 5. IGBT Turn-on. Typical turn-on waveform 6. IGBT Turn-off. Typical turn-off waveform 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Time 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Time 7. Variation of with 8. Variation of sense voltage with using external bias of 4.3KΩ, 20 40 60 80 100 120 (k _ Ω ) 20 40 60 80 100 120 (°C) V se ns e (V ) . 10. minimum Bootstrap Capacitor value Vs 9. Estimated maximum IGBT junction with 1.5 3 4.5 6 7.5 9 10.5 12 13.5 15 16.5 18 Frequency ( 10 15 90 100 110 120 130 140 ( °C ) 11. Switching Parameter 11a. Input to Output turn-on delay 11b. Input to turn-off delay 11c. Diode Reverse IC 10% tf 90% IC 10% CT1. Switching Loss CT2. S.C.SOA CT3. R.B.SOA Voltage on the IGBT Voltage on the IGBT pin in mm 1 - Marking for pin 1 Product Part Number 3- Lot and Date code 1 note 2 note 3 For mounting see option in mm 1 - Marking for pin 1 Product Part Number 3- Lot and Date code 1 note 2 note 3 IR WORLD 233 Kansas St., El Segundo, 90245, USA Tel: (310) Fax: (310) us at for sales contact F, and are subject to change without notice